1. Field of the Invention
The present invention relates to a self-synchronizing scrambler which comprises n clock shift register stages for generating a signal having a scrambler period of 2.sup.n -1 bits, whereby the output of at least one shift register stage is connected to the input of a modulo-2 adder.
2. Description of the Prior Art
Pulse patterns which have a disturbing DC component or whose energy component is particularly high at certain discrete frequencies can occur in digital signal transmission. In order to avoid these pulse patterns, the digital signal to be transmitted is scrambled at the transmitting side by a modulo-2 addition with a pseudo-random sequence. The descrambling occurs at the receiving side by a further modulo-2 addition with the pseudo-random sequence which was employed at the transmitting side. The synchronization of the pseudo-random generators employed at the transmitting and receiving sides, which is thereby necessary, can be avoided by employing free-wheeling and, therefore, self-synchronizing scrambler and descrambler arrangements.
The expansion of digital telecommunications networks has lead to the installation of transmission devices for signals having very high modulation rates between central points of the network. Resulting therefrom, however, is the necessity of constructing scramblers and descramblers for digital signals having a high clock frequency.
"Siemens Forschungs-und Entwicklungsberichte", Vol. 6, No. 1, 1977, pp. 1-5, fully incorporated herein by this reference, discloses a possibility for constructing scramblers for pulse code modulated (PCM) signals having a high clock frequency. The PCM signals having a high bit sequence are scrambled in a plurality of parallel channels having a lower bit repetition frequency and the signals which arise are combined by multiplexing. The receiving side is constructed in an analogous manner, the parallel descrambling occurring in a plurality of channels following a demultiplexer. In addition to the high expense, the necessity of synchronizing multiplexers and demultiplexers with one another therefore also arises.